Updated 27 October 2026
ZilionX is an active engineering project. Milestones below distinguish implemented and measured work from current development and planned evaluation.
Vision simulation verification · 27 October 2026
A frozen trained encoder met its predeclared targets on a registered procedural image-relation evaluation. CPU, integer-reference and SDK/RTL classifications were correct on 64/64 images in each paired group.
Verified simulation path: Host → public SDK → simulated DMA → RTL encoder → SDK → host. Patch embedding, position embedding, pooling and the classification head remain on the host.
All final RTL encoder outputs matched the integer reference byte-for-byte. Three replay checks passed, each in a persistent SDK process with one model load. The evaluation reused a previously verified simulator build; internal RTL layer checkpoints were not directly compared.
Original images, relevant-patch flips and distractor-patch flips each achieved 64/64 correct classifications. These are 64 base images with paired interventions, not 192 independent samples. The tiny profile uses four patch tokens, D=8, FFN=32, two layers, four-head MHA, pre-LayerNorm and GELU.
Development included conversion clipping checks, counterfactual failures and per-layer attention controls. Earlier one-layer registered evaluations missed their accuracy targets; those results remain documented. Different models and batches do not establish a controlled superiority comparison.
Read the vision verification report · Download the public vision summary
Limits: Procedural toy images, not external real-world data. This is not full-size or pretrained ViT validation, drone or automotive readiness, safety certification, physical FPGA execution or measured board performance. Vision verification is local engineering work, not a new Developer Portal job capability.
Simulation verification · 24 October 2026
A fresh-directory engineering run passed all 12 workflow stages: two fixture/build stages and ten verification stages. The tests cover a restricted eight-layer synthetic transformer configuration and separate one-layer trained toy tasks.
Simulation dataflow: Host → public SDK → simulated DMA → RTL computation → SDK → host.
The public-SDK path loads model and input data, executes the transformer RTL and retrieves outputs for exact comparison against the integer reference. The scope is 4 tokens, hidden dimension 8, FFN dimension 32, 8 layers and 4 query / 2 KV heads. Persistent sessions process successive inputs without reloading the model.
Checks cover requantization boundaries, extreme inputs, GQA address routing, model replacement and interrupted-load recovery, standalone DMA and memory-fabric backpressure, and integrated inference under two competing weight-read schedules. Standalone and integrated results have different scopes.
Character-cycle tests verified 24 generation steps; context-copy tests verified 64 context-dependent answers. A persistent SDK session also generated three successive cycle tokens from returned RTL outputs. Embeddings, final normalization and vocabulary scoring remain on the CPU. These are toy training-task checks, not general-language evaluation.
The completed run recorded accelerator source e023267715f6bb6467e66d6f84b8349b12708a5c. Its suite runner was committed afterward as b7899e1; the completed run must not be relabelled as testing that later commit. Results are engineering-run regressions, not independent certification.
Read the verification report · Download the public result summary
Limits: Agreement is bit-exact against the integer reference for tested inputs. The suite is finite, not exhaustive. This milestone does not demonstrate physical FPGA execution, model-scale language inference, measured board throughput or power. Historical routed timing results below apply to their own configurations, not this new suite.
Historical checkpoint · 23 October 2026
The Stage 3N GQA/RoPE checkpoint passed seven eight-layer golden-vector suites: 56/56 layer comparisons. The test scope is tiny: 4 tokens × D=8 × 8 layers, with four query heads and two KV heads (4Q/2KV). Streaming, overlapped preload, weight bypass, descriptor and queued descriptor DMA have verified checkpoints.
The four-phase GQA/RoPE implementation reports 22.08 MHz routed Fmax against a 20 MHz target on ECP5. Synthesis and place-and-route have been completed for this scoped configuration. Physical-board and complete-system validation remain ahead.
Work through 23 October adds calibrated Qwen2 checkpoint conversion to package v4, guarded scaled RTL execution, parameter and requantization DMA loading, and attention/FFN requantization support. Integration and broader numerical verification remain in progress.
The October 23 commits establish implementation progress. They do not establish full Qwen2 inference, model accuracy, model-scale hardware validation or measured board throughput. Earlier verification results apply to their stated checkpoints.
Python golden model, fixed-point components and integrated Transformer datapath with memory fabric. Historical Stage 3K, 3L and October 3 cycle measurements remain available on Benchmarks.
Seven eight-layer GQA/RoPE suites and 56/56 layer comparisons in the tiny 4Q/2KV scope. Verified tags cover streaming DMA, overlapped preload, weight bypass, descriptor DMA and queued descriptor DMA.
ECP5 out-of-context implementation includes a four-phase GQA/RoPE result of 22.08 MHz against a 20 MHz target. This is tool-based evidence; physical-board validation remains outstanding.
Calibrated Qwen2 checkpoint conversion to package v4; guarded scaled RTL execution; parameter and requantization DMA loading; attention output/context requantization and score correction; FFN gate/up/down and SwiGLU multiply requantization, with associated record arbitration. Commit evidence is listed in the 23 October checkpoint.
Extend tested seeds, numerical configurations and failure schedules. Add stronger internal overflow and transfer-integrity instrumentation. Existing passes do not establish arbitrary backpressure coverage or exhaustive correctness.
Validate board operation and complete-system interfaces, then measure performance and power for the tested hardware setup. Simulation cycle counts and host run times are not board measurements.
Extend the verified tiny vision profile toward larger image and token geometries, trained model import and broader datasets. Representative language workloads also remain ahead. The current toy results do not establish production workload accuracy.
Read benchmark scope and measured cycle counts →
Available preview: Cloudflare-hosted frontend, Clerk sign-in, authenticated Pages Functions/D1 workflow, preliminary configuration reports, mock jobs and testing requests. A restricted, pinned synthetic fixture can undergo manually approved public-SDK-backed RTL simulation on an operator-started Ubuntu runner.
Separate local verification: the combined stress suite, trained toy-generation regressions and vision workflows are not yet integrated into portal jobs. Existing job results retain their recorded scope. General-language inference and FPGA execution are not available. Read the preview scope.