# Accelerator Simulation Verification

Report date: 24 October 2026 (Australia/Sydney)

## Result

PASS: all 12 stages in one fresh-directory engineering run. This comprises two setup stages and ten verification stages; it is not a count of 12 independent testbenches.

Tested accelerator source: `e023267715f6bb6467e66d6f84b8349b12708a5c`.
Suite runner committed after the run: `b7899e1`.
The completed run is attributed to its recorded source revision, not retroactively to the runner commit.

Evidence basis: project engineering console output and the completed suite report. This is not independent certification.

## Dataflow and Configuration

Host -> public SDK -> simulated DMA -> RTL computation -> SDK -> host.

The eight-layer synthetic configuration uses four tokens, hidden dimension 8, FFN dimension 32, four query heads and two KV heads. Separate trained character-cycle and context-copy tests use one layer, with CPU-side embeddings, final normalization and vocabulary scoring.

## Passed Stages

- PASS (setup): prepare-eight-layer-source
- PASS (setup): build-eight-layer-baseline
- PASS (verification): run_requantization_stress
- PASS (verification): run_gqa_address_stress
- PASS (verification): run_dma_backpressure_stress
- PASS (verification): run_memory_fabric_stress
- PASS (verification): run_eight_layer_input_stress
- PASS (verification): run_eight_layer_cache_stress
- PASS (verification): run_eight_layer_contention
- PASS (verification): eight-layer-session-protocol
- PASS (verification): trained-cycle
- PASS (verification): trained-context-copy

## Coverage Boundaries

- Requantization stress compares the Python reference and RTL against a separate integer oracle.
- Eight-layer input stress checks exact final outputs for numerical-extreme patterns and replay.
- GQA checks isolate address routing, enable holds, completion and reset; they do not verify every attention datapath operation.
- Model-replacement and load-abort recovery stress runs at simulator-adapter level, not through public-SDK model replacement.
- Standalone DMA and six-client memory-fabric tests exercise their documented handshake schedules.
- Integrated eight-layer contention uses checked, read-only weight traffic and raw-client response stalls in a temporary instrumented adapter. It does not insert arbitrary stalls on every internal client.
- Trained toy tasks check their training-task behavior, not unseen-language generalization.
- The persistent generation regression checks three output-dependent generation steps in one public-SDK session.

## Reproduction

The suite runner is stored at `tests/run_accelerator_stress_suite.py` in TLLM. With the compatible Python dependencies and OSS CAD Suite/Verilator environment configured, run from the checkout:

```bash
python3 tests/run_accelerator_stress_suite.py --root "$PWD"
```

The runner creates fresh fixtures/builds, stops on failure, and records logs, source hashes and tool versions. The runner commit above identifies the subsequently saved reproduction entry point; a new run records its own source commit and provenance.

## Limitations

These results establish agreement for finite tested inputs and schedules, not exhaustive correctness or mathematical proof. Exact output agreement is against the integer reference; it is not a model-accuracy percentage.

No physical FPGA execution, general-purpose language inference, board throughput, power or exhaustive internal-overflow coverage is established. Host elapsed times are not accelerator performance measurements. Historical place-and-route results refer to their own configurations.

The combined suite and trained toy-generation tests are local engineering regressions, not portal job results. Portal-connected synthetic fixture results retain their original scope.

## Public Evidence

This public report and its JSON companion summarize the supplied suite result. Private artifact paths, host timings and raw provenance are intentionally not published. Per-stage raw logs are not included in this public bundle.