ZilionX™ Transformer Engine
ZilionX is Avilicon’s Transformer accelerator RTL. Its integrated layer datapath brings together attention, projection, normalization, residual operations and feed-forward processing. Stage 3N integrates the memory fabric with the compute engines; FPGA implementation-tool results now complement the RTL benchmark work.
Public subsystem overview · updated 23 October 2026. Detailed measurements and test conditions are available in Benchmarks; development milestones are tracked in Progress.
Model preparation · quantization metadata · package v4
Package validation · configuration · DMA requests
Connections indicate functional relationships; the FPGA pathway represents implementation and validation milestones. See Benchmarks for measurements and defined test configurations.
The layer scheduler coordinates compute activity and data transfers. The memory fabric serves the engines, while DMA provides a loading and transfer path into the memory subsystem.
Arrows distinguish control from data movement. This conceptual view does not specify physical placement, bus topology, memory-bank mapping or a production host interface.
Functional overview of the integrated layer; not a cycle-accurate schedule or a specification of every supported model topology.
The attention path uses fixed-point arithmetic and includes softmax and rotary positional embeddings (RoPE) in the scoped GQA/RoPE checkpoint. The ECP5 implementation snapshot below includes a grouped-query attention (GQA) configuration with four query heads and two key/value heads.
Historical baseline measurements include linear operations and GELU. Recent implementation work adds runtime FFN gate/up/down and SwiGLU multiply requantization; the newer package-v4 path is under verification.
Layer normalization and residual transfers are included in the historical integrated layer benchmark. Their inclusion establishes the benchmark’s scope, rather than end-to-end model validation.
The Stage 3M memory fabric is integrated with the Transformer RTL in Stage 3N. It coordinates access to working data alongside the compute engines, with DMA supporting data loading and transfers. Its architectural purpose is to improve data availability and reduce avoidable waiting during layer execution.
That purpose is distinct from a measured performance gain. DMA loading, memory transactions and compute stalls must be assessed within a stated benchmark configuration. Resource use and memory inference must likewise be read from the corresponding synthesis and implementation reports.
Verified DMA milestones include streaming, overlapped preload, weight bypass, descriptor loading and queued descriptors. These apply to their published small-configuration checkpoints.
See Benchmarks for the published measurement scope and comparisons. No external-memory bandwidth or production-interface capability is inferred from this subsystem diagram.
As of 23 October, the development path includes calibrated Qwen2 checkpoint conversion into package v4, guarded scaled RTL execution and parameter/requantization DMA-loading implementation, under integration verification. Recent attention work covers output and context requantization, score correction and associated record arbitration. FFN work covers gate/up/down and SwiGLU multiply requantization.
These are implemented integration capabilities under verification. The earlier seven-suite, 56/56 GQA/RoPE result does not validate all package-v4 changes. Full Qwen2 inference and model-scale hardware validation remain unestablished.
Control coordinates the integrated engines and their data delivery. Verification evidence applies to the exercised configurations and test paths; it does not establish unrestricted support for arbitrary Transformer models.
Fault detection and recovery remain design goals requiring dedicated verification. The implementation results below do not demonstrate fault tolerance, recovery coverage or reliability on physical hardware.
The 13 October default and GQA results are retained below alongside the later four-phase GQA/RoPE checkpoint. Each frequency belongs to its own out-of-context place-and-route run; the October 23 package-v4 changes have no new routed result reported here.
| Configuration | Routed Fmax | Reported target status |
|---|---|---|
| Default configuration | 23.61 MHz | Reference result |
| 4Q/2KV GQA 4 query heads / 2 key-value heads | 21.72 MHz | 20 MHz target met |
| 4Q/2KV GQA + four-phase RoPE · 15 October | 22.08 MHz | 20 MHz target met |
Implementation evidence, not board measurements. These figures are place-and-route timing estimates for the stated configurations. They are not a general ZilionX operating frequency, measured physical-board performance, full-system timing closure or an ASIC performance prediction.
The GQA result meets the reported 20 MHz target in its routed run. Timing results alone do not establish numerical correctness, model accuracy, throughput, power consumption or memory bandwidth. Refer to Benchmarks for available implementation details and supporting evidence.
No end-to-end Tiny LLM or Vision Transformer (ViT) throughput claim is established by the present layer test configuration.
The first workload direction is compact language Transformers. Next development priorities are physical FPGA validation, further memory/DMA and performance characterization, and broader numerical and workload verification. Vision Transformers are a planned extension after the current implementation and benchmark work.
These are development directions, not committed delivery dates or demonstrated capabilities. Follow Progress for milestone updates.
This page describes subsystem roles, supported operations within the reported scope, and implementation milestones. Proprietary RTL, detailed controller state machines, scheduling mechanisms, bank mapping, arbitration algorithms, netlists and internal verification vectors are outside this public overview.
For discussions about ZilionX IP evaluation, integration requirements or licensing, contact Avilicon. Evaluation scope and access to technical material can be agreed directly.