Architecture
See the datapath and memory overview.
About Avilicon
Building Transformer hardware for the edge
Avilicon is developing ZilionX™, Australian semiconductor intellectual property for Transformer inference on constrained edge systems. The work is based in Sydney, Australia.
Our engineering approach
Development began with a Python golden simulator and progressed through fixed-point RTL engines to an integrated Transformer datapath. We verify arithmetic and control behaviour in simulation, measure cycle counts, then use those measurements to guide architecture changes.
The Stage 3M memory fabric is integrated into Stage 3N. Scoped GQA/RoPE and DMA verification and ECP5 out-of-context place-and-route results are available. October 23 package-v4 integration is under verification; physical-board and representative model evaluation remain ahead. Published benchmarks describe simulation and implementation-tool results and their limits.
Explore the project
Evaluation and integration discussions
ZilionX remains in development: scoped RTL verification and FPGA implementation-tool evidence support the next integration stage. We welcome discussions about prospective IP evaluation, integration requirements and licensing scope. Access and readiness are agreed directly; the portal preview does not provide SDK or FPGA execution.