Advanced Versatile Inference Silicon
Developing an inference accelerator for Transformer workloads on constrained edge systems. The current RTL integrates attention, feed-forward and normalization paths. The Stage 3M memory fabric has been integrated with the Transformer RTL in Stage 3N. Synthesis and implementation analysis are the next validation steps.
ZilionX development
The hardware data path and the software path are advancing together. Each milestone below states what has been built and what is still being evaluated.
The Stage 3M memory fabric is implemented and integrated with the Transformer RTL. The integrated RTL records 30,945 compute cycles in the reported eight-layer test. Synthesis, memory inference and separate DMA loading measurements are next.
Follow integration progressThe first SDK work defines and validates a ZilionX model package so model data can enter a controlled evaluation flow. Runtime integration, representative model execution and FPGA evaluation are subsequent milestones.
Discuss an evaluationFixed-point attention and softmax RTL alongside integrated feed-forward, normalization and residual paths.
Stage 3M memory fabric integrated with the Transformer RTL. Synthesis will assess memory inference and resource use; larger stress runs and separate DMA loading measurements are next.
Cycle-level simulation today; FPGA evaluation and representative model workloads are future milestones.
Architecture overview explains the blocks and intended memory integration. Benchmarks provides the measured cycle counts and test scope. Progress separates completed work from active and planned work.