Advanced Versatile Inference Silicon
ZilionX™ is an Australian-developed semiconductor IP architecture for Transformer inference on constrained edge systems. The integrated RTL combines attention, feed-forward processing, normalization and residual operations with a shared memory fabric and DMA-assisted data movement. Stage 3N has progressed from verified RTL simulation and DMA benchmarking to synthesis and initial FPGA place-and-route evaluation, including grouped-query attention (GQA).
Memory-fabric integration, streaming DMA loader testing and the published legacy golden-vector regressions are complete. The four-token, D=8, eight-layer streaming checkpoint records 31,553 inference cycles and 33,892 load-to-result cycles with sequential cache warm-up. A later overlapped warm-up checkpoint records 33,787 load-to-result cycles. These are RTL simulation results for a small verification configuration.
Initial ECP5-85K out-of-context placement and routing completed for the baseline and 4Q/2KV GQA configurations; both meet the 20 MHz timing constraint. Physical FPGA-board validation and representative model execution remain future milestones. Review checkpoint scope and results →
ZilionX development
The hardware data path and the software path are advancing together. Each milestone below states what has been built and what is still being evaluated.
The Stage 3M memory fabric is integrated with the Stage 3N Transformer engine, coordinating memory access and DMA-assisted loading. Integrated RTL regression and loader tests passed for the published configurations. Synthesis and initial FPGA place-and-route results support continued timing, resource and memory optimisation.
Follow integration progressThe first SDK work defines and validates a ZilionX model package so model data can enter a controlled evaluation flow. SDK runtime integration, representative model execution and board-based evaluation are subsequent milestones. This is a model-package foundation, not a production-ready runtime.
Discuss an evaluationIntegrated fixed-point attention, softmax, feed-forward, normalization and residual processing.
Shared memory fabric, streaming DMA loading and cache preload, with simulation measurements scoped to each published checkpoint.
Evaluation of query and key/value configurations, including 4Q/2KV GQA. Independent numerical tests passed; full-stack golden-output comparison for the integrated 4Q/2KV traffic run remains outstanding.
Synthesis, resource analysis and routed timing evaluation, ahead of physical FPGA-board validation and representative model workloads.
Stage 3N · Lattice ECP5-85K · out-of-context placement and routing.
| Configuration | Routed Fmax | 20 MHz constraint |
|---|---|---|
| Baseline · 1Q/1KV | 23.61 MHz | Met |
| GQA · 4Q/2KV | 21.72 MHz | Met |
These are FPGA tool-based out-of-context timing results, not physical-board performance measurements. Board-level I/O, complete-system timing and external-memory interface timing are excluded. They do not establish model throughput.
Architecture overview explains the Transformer compute blocks, shared memory fabric, DMA integration and development scope. Benchmarks provides simulation checkpoints, synthesis resources and routed timing results with their measurement limits. Progress tracks completed, active and planned work.
Avilicon is developing ZilionX as licensable semiconductor intellectual property for future edge AI systems. We welcome technical discussions with semiconductor companies, research organisations and potential evaluation partners.