Advanced Versatile Inference Silicon
ZilionX™ is an Australian-developed semiconductor IP architecture for Transformer inference on constrained edge systems. The integrated RTL combines attention, feed-forward processing, normalization and residual operations with a shared memory fabric and DMA-assisted data movement. Stage 3N has progressed from verified RTL simulation and DMA benchmarking to synthesis and initial FPGA place-and-route evaluation, including grouped-query attention (GQA).
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SDK and FPGA execution are planned. Current jobs demonstrate the evaluation workflow. The optional Ubuntu runner checks connectivity only and currently returns “SDK unavailable.” No SDK or FPGA execution is connected.
Development checkpoint · 23 October 2026
The Stage 3N GQA/RoPE checkpoint passed seven eight-layer golden-vector suites: 56/56 layer comparisons. The test scope is tiny: 4 tokens × D=8 × 8 layers, with four query heads and two KV heads (4Q/2KV). Streaming, overlapped preload, weight bypass, descriptor and queued descriptor DMA have verified checkpoints.
The four-phase GQA/RoPE implementation reports 22.08 MHz routed Fmax against a 20 MHz target on ECP5. Synthesis and place-and-route have been completed for this scoped configuration. Physical-board and complete-system validation remain ahead.
Work through 23 October adds calibrated Qwen2 checkpoint conversion to package v4, guarded scaled RTL execution, parameter and requantization DMA loading, and attention/FFN requantization support. Integration and broader numerical verification remain in progress.
The October 23 commits establish implementation progress. They do not establish full Qwen2 inference, model accuracy, model-scale hardware validation or measured board throughput. Earlier verification results apply to their stated checkpoints.
ZilionX development
The hardware data path and the software path are advancing together. Each milestone below states what has been built and what is still being evaluated.
The Stage 3M memory fabric is integrated with the Stage 3N Transformer engine, coordinating memory access and DMA-assisted loading. Integrated RTL regression and loader tests passed for the published configurations. Synthesis and initial FPGA place-and-route results support continued timing, resource and memory optimisation.
Follow integration progressNot connected to portal execution.
The software path now includes calibrated Qwen2 checkpoint conversion to package v4 and guarded scaled RTL execution. Parameter and requantization loading and attention/FFN scaling are implemented and under verification. Representative model execution and board-based evaluation remain subsequent milestones.
Discuss an evaluationIntegrated fixed-point attention, softmax, feed-forward, normalization and residual processing.
Shared memory fabric, streaming DMA loading and cache preload, with simulation measurements scoped to each published checkpoint.
The later Stage 3N GQA/RoPE checkpoint passed seven eight-layer suites and 56/56 layer comparisons in the stated tiny 4Q/2KV configuration. Earlier traffic-only checkpoints retain their original scope.
Synthesis, resource analysis and routed timing evaluation, ahead of physical FPGA-board validation and representative model workloads.
Stage 3N · Lattice ECP5-85K · out-of-context placement and routing.
| Configuration | Routed Fmax | 20 MHz constraint |
|---|---|---|
| Baseline · 1Q/1KV | 23.61 MHz | Met |
| GQA · 4Q/2KV | 21.72 MHz | Met |
| GQA + four-phase RoPE · 15 October | 22.08 MHz | 20 MHz target met |
These are FPGA tool-based out-of-context timing results, not physical-board performance measurements. Board-level I/O, complete-system timing and external-memory interface timing are excluded. They do not establish model throughput.
Architecture overview explains the Transformer compute blocks, shared memory fabric, DMA integration and development scope. Benchmarks provides simulation checkpoints, synthesis resources and routed timing results with their measurement limits. Progress tracks completed, active and planned work.
Avilicon is developing ZilionX as licensable semiconductor intellectual property for future edge AI systems. We welcome technical discussions with semiconductor companies, research organisations and potential evaluation partners.
Our development path connects model conversion and calibration, SDK/runtime integration, Transformer RTL, and memory fabric/DMA. Representative model execution and physical FPGA-board evaluation remain planned milestones.