Golden model
Python reference simulator for checking arithmetic and functional behavior.
Updated 29 September 2026
Development progress
ZilionX is an active engineering project. Milestones below distinguish implemented and measured work from current development and planned evaluation.
Completed
RTL components
Fixed-point arithmetic, attention and softmax work with component-level verification.
Transformer datapath
Integrated attention, normalization, residual and feed-forward paths. An eight-layer simulation baseline recorded 31,906 cycles for its defined test configuration.
Memory fabric implementation
The memory fabric RTL is implemented. Its impact on the integrated accelerator will be measured in Stage 3N.
In development
Stage 3N
RTL integration and benchmark
Integrating the Stage 3M memory fabric with the Transformer RTL and measuring cycles and data movement against the pre-integration Stage 3K baseline. Results will be published after verification.
Planned
FPGA evaluation
Implement and measure the design on an FPGA, including timing closure, memory and logic resources, and power where measurable.
Representative workloads
Move from the current small test configuration toward compact language Transformer workloads and, later, Vision Transformer inference.
Developer integration
Build an evaluation path and minimal software interface after the hardware baseline is stable.