Stage 3K baseline · RTL simulation
Benchmarks
This pre-Stage 3M integration baseline measures cycle counts for an eight-layer integrated Transformer test configuration. It is a simulation result, not measured silicon or FPGA throughput and not an end-to-end 0.5B–3B parameter model result.
Total simulated cycles
Transformer layers in the test
Assumed clock period for the simulation configuration; not a verified FPGA frequency
Cycle breakdown
| Measured category | Cycles / count |
|---|---|
| Total run | 31,906 |
| Attention | 13,073 |
| Feed-forward network | 17,504 |
| Layer normalization | 1,288 |
| Control and other | 41 |
| Residual transactions | 256 |
| Output transactions | 256 |
The four cycle categories sum to the total run. Transaction counts describe the test configuration and are not cycle categories.
Interpretation and limits
The FFN accounts for approximately 55% of measured cycles and attention approximately 41%. These figures expose where this particular configuration spends cycles; they do not establish TOPS, tokens per second, power efficiency, external-memory bandwidth or comparative performance against commercial devices.
Dimensions and model coverage must accompany any future workload-level performance claim. Stage 3N is integrating and benchmarking the Stage 3M memory fabric against this pre-integration baseline. Memory traffic, stalls, bank conflicts and compute utilisation have not yet been published; the current figures do not measure those quantities.
Next evidence
Publish a reproducible configuration with model dimensions, precision, stimuli and clocks; report verified Stage 3N results beside this pre-integration baseline using the same test configuration; then validate frequency, resources and power on an FPGA.